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DISCRETE SEMICONDUCTORS
DATA SHEET
PHC20306 Complementary enhancement mode MOS transistor
Objective specification File under Discrete Semiconductors, SC13b 1998 Feb 18
Philips Semiconductors
Objective specification
Complementary enhancement mode MOS transistor
FEATURES * Very low on-state resistance * High-speed switching * No secondary breakdown. APPLICATIONS * Motor and actuator driver * Power management * Synchronized rectification. DESCRIPTION One N-channel and one P-channel enhancement mode MOS transistor in an 8-pin SOT96-1 (SO8) plastic package. CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling.
1 4 s1 8 handbook, halfpage 5 d1 d1
PHC20306
PINNING - SOT96-1 (SO8) PIN 1 2 3 4 5 6 7 8 SYMBOL s1 g1 s2 g2 d2 d2 d1 d1 DESCRIPTION source 1 gate 1 source 2 gate 2 drain 2 drain 2 drain 1 drain 1
d2 d2
MAM118
g1
s2
g2
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA SYMBOL Per channel VDS drain-source voltage (DC) N-channel P-channel VSD source-drain diode forward voltage N-channel P-channel VGSO VGSth gate-source voltage (DC) gate-source threshold voltage N-channel P-channel ID drain current (DC) N-channel P-channel RDSon drain-source on-state resistance N-channel P-channel Ptot 1998 Feb 18 total power dissipation VGS = 10 V; ID = 4 A VGS = -10 V; ID = -2.8 A Ts = 80 C 2 - - - 30 65 3.5 m m W VDS = VGS; ID = 1 mA VDS = VGS ; ID = -1 mA Ts = 80 C - - 8.2 -5.6 A A 1 -1 - - VGD = 0; IS = 1.25 A VGD = 0; IS = -1.25 A open drain - - - 1 -1.3 20 V V V V V V - - 30 -30 V V PARAMETER CONDITIONS MIN. MAX. UNIT
Philips Semiconductors
Objective specification
Complementary enhancement mode MOS transistor
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL Per channel VDS drain-source voltage (DC) N-channel P-channel VGSO ID gate-source voltage (DC) drain current (DC) N-channel P-channel IDM peak drain current N-channel P-channel Ptot total power dissipation Ts = 80 C; note 3 Tamb = 25 C; note 4 Tamb = 25 C; note 5 Tamb = 25 C; note 6 Tstg Tj IS storage temperature operating junction temperature Ts = 80 C - - note 2 - - note 2 - - - - - - -55 -55 open drain Ts = 80 C; note 1 - - - - - PARAMETER CONDITIONS MIN.
PHC20306
MAX.
UNIT
30 -30 20 8.2 -5.6 33 -22.5 3.5 2.6 1.1 1.5 +150 +150
V V V A A A A W W W W C C
Source-drain diode source current (DC) N-channel P-channel ISM peak pulsed source current N-channel P-channel Notes 1. Ts is the temperature at the soldering point of the drain lead. 2. Pulse width and duty cycle limited by maximum junction temperature. 3. Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 3.5 W at the same time. 4. Maximum permissible dissipation per MOS transistor. Device mounted on a printed-circuit board with an Rth a-tp (ambient to tie-point) of 27.5 K/W. 5. Maximum permissible dissipation per MOS transistor. Device mounted on a printed-circuit board with an Rth a-tp (ambient to tie-point) of 90 K/W. 6. Maximum permissible dissipation if only one MOS transistor dissipates. Device mounted a on printed-circuit board with an Rth a-tp (ambient to tie-point) of 90 K/W. 3.5 -2.7 14 -10.8 A A A A
1998 Feb 18
3
Philips Semiconductors
Objective specification
Complementary enhancement mode MOS transistor
THERMAL CHARACTERISTICS SYMBOL Rth j-s PARAMETER thermal resistance from junction to soldering point VALUE 20
PHC20306
UNIT K/W
CHARACTERISTICS Tj = 25 C unless otherwise specified. SYMBOL Per channel V(BR)DSS drain-source breakdown voltage N-channel P-channel VGSth gate-source threshold voltage N-channel P-channel IDSS drain-source leakage current N-channel P-channel IGSS gate leakage current N-channel P-channel RDSon drain-source on-state resistance N-channel P-channel Ciss input capacitance N-channel P-channel Coss output capacitance N-channel P-channel Crss reverse transfer capacitance N-channel P-channel QG total gate charge N-channel P-channel QGS gate-source charge N-channel P-channel VDD = 15 V; ID = 4 A VDD = -15 V; ID = -2.8 A - - 2 tbf - - nC nC VGS = 10 V; VDD = 15 V; ID = 4 A - 16 tbf 30 tbf nC nC VGS = -10 V; VDD = -15 V; ID = -2.8 A - VGS = 0; VDS = 24 V; f = 1 MHz VGS = 0; VDS = -24 V; f = 1 MHz - - 110 tbf 135 tbf pF pF VGS = 0; VDS = 24 V; f = 1 MHz VGS = 0; VDS = -24 V; f = 1 MHz - - 260 tbf 320 tbf pF pF VGS = 0; VDS = 24 V; f = 1 MHz VGS = 0; VDS = -24 V; f = 1 MHz - - 700 tbf 850 tbf pF pF VGS = 4.5 V; ID = 2 A VGS = 10 V; ID = 4 A VGS = -4.5 V; ID = -1.4 A VGS = -10 V; ID = -2.8 A - - - - - - - - 45 30 100 65 m m m m VGS = 0; VDS = 24 V VGS = 0; VDS = -24 V VGS = 20 V; VDS = 0 - - - - 100 100 nA nA - - - - 100 -100 nA nA VGS = VDS ; ID = 1 mA VGS = VDS ; ID = -1 mA 1 -1 - - - - V V VGS = 0; ID = 10 A VGS = 0; ID = -10 A 30 -30 - - - - V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1998 Feb 18
4
Philips Semiconductors
Objective specification
Complementary enhancement mode MOS transistor
SYMBOL QGD PARAMETER gate-drain charge N-channel P-channel Switching times td(on) turn-on delay time N-channel P-channel tr rise time N-channel P-channel ton turn-on switching time N-channel P-channel td(off) turn-off delay time N-channel P-channel tf fall time N-channel P-channel toff turn-off switching time N-channel P-channel Source-drain diode VSD source-drain diode forward voltage N-channel P-channel trr reverse recovery time N-channel P-channel IS = 1.25 A; di/dt = -100 A/s IS = -1.25 A; di/dt = 100 A/s - - 45 tbf VGD = 0; IS =1.25 A VGD = 0; IS = -1.25 A - - - - VGS = 10 to 0 V; VDD = 20 V; ID = 1 A; Rgen = 6 VGS = -10 to 0 V; VDD = -20 V; ID = -1 A; Rgen = 6 - - 40 tbf VGS = 0 to 10 V; VDD = 20 V; ID = 1 A; Rgen = 6 VGS = -10 to 0 V; VDD = -20 V; ID = -1 A; Rgen = 6 - - 9 tbf VGS = 10 to 0 V; VDD = 20 V; ID = 1 A; Rgen = 6 VGS = -10 to 0 V; VDD = -20 V; ID = -1 A; Rgen = 6 - - 19 tbf VGS = 0 to 10 V; VDD = 20 V; ID = 1 A; Rgen = 6 VGS = 0 to -10 V; VDD = -20 V; ID = -1 A; Rgen = 6 - - 17 tbf VGS = 10 to 0 V; VDD = 20 V; ID = 1 A; Rgen = 6 VGS = 0 to -10 V; VDD = -20 V; ID = -1 A; Rgen = 6 - - 21 tbf VGS = 0 to 10 V; VDD = 20 V; ID = 1 A; Rgen = 6 VGS = 0 to -10 V; VDD = -20 V; ID = -1 A; Rgen = 6 - - 8 tbf VDD = 15 V; ID = 4 A VDD = -15 V; ID = -2.8 A - - CONDITIONS MIN.
PHC20306
TYP. 6.5 tbf
MAX. UNIT - - nC nC
- -
ns ns
- -
ns ns
25 tbf
ns ns
- -
ns ns
- -
ns ns
60 tbf
ns ns
1 -1.3 - -
V V ns ns
1998 Feb 18
5
Philips Semiconductors
Objective specification
Complementary enhancement mode MOS transistor
PACKAGE OUTLINE SO8: plastic small outline package; 8 leads; body width 3.9 mm
PHC20306
SOT96-1
D
E
A X
c y HE vMA
Z 8 5
Q A2 A1 pin 1 index Lp 1 e bp 4 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 0.069 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.050 0.041 0.228 0.016 0.024
0.028 0.004 0.012
8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03S JEDEC MS-012AA EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-05-22
1998 Feb 18
6
Philips Semiconductors
Objective specification
Complementary enhancement mode MOS transistor
DEFINITIONS Data Sheet Status Objective specification Preliminary specification Product specification Limiting values
PHC20306
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1998 Feb 18
7
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
135108/00/01/pp8
Date of release: 1998 Feb 18
Document order number:
9397 750 03218

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